Wa_curated: "curated:donotuseinexternalfilters/intellectualproperty", Wa_primarycontenttagging: "primarycontenttagging:intelfpgas/intelfpgaintellectualproperty/interfaceprotocols,primarycontenttagging:intelfpgas/intelprogrammabledevices,primarycontenttagging:intelfpgas/intelprogrammabledevices/intelstratix/stratixivfpgas,primarycontenttagging:intelfpgas/intelprogrammabledevices/intelstratix/stratixvfpgas,primarycontenttagging:intelfpgas/intelprogrammabledevices/intelarria/arriavfpgasandsocfpgas", Wa_emtcontenttype: "emtcontenttype:designanddevelopmentreference/developerguide/developeruserguide", MII data RX connection, starting with the LSB and least significant word, outputting a 5-word data stream. This signal is available as an output status signal in MAC and PHY IP core variations as well as in PHY-only variations. Media independent interface (MII) data TX connection, starting with the least significant bit (LSB).Īsserted upon valid TX to MII connection.Īsserted when TX data bus is ready for MII connection.Īsserted when TX lanes are stable and deskewed. In the table, = 2 for the 40GbE IP core and = 5 for the 100GbE IP core. In addition, the tx_lanes_stable output signal from the PHY component is available to provide status information to user logic in PHY-only IP core variations and in MAC and PHY IP core variations. The MAC–PHY connection interface is exposed in the 40‑100GbE MAC-only and PHY-only IP core variations. MAC to PHY and PHY to MAC TX and RX Signals
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